In the fabrication of electronic circuits, one technique utilized to increase production yield is to provide redundant circuit elements on the chip to allow for replacement of key circuit elements which prove to be defective. During testing of the chip, the defective portion of the circuit is identified and the redundant circuit element, if one exists, is activated by opening an associated fuse or similar mechanism.
Redundancy is especially suited for repetitive circuits having a large number of repeating elements arranged in some form of an array, such that one redundant circuit can replace a single defect in any of a large number of circuit elements. One such device is a semiconductor memory comprised primarily of memory cells. These memory cells are arranged in rows and columns wherein the redundant cell would be either a row of memory cells or a column of memory cells. If, for example, one cell in a given column was determined to be defective, this would classify the device as defective. This defective column could then be replaced by a redundant column and the device would be fully operational. A typical memory would have, for example, 256 rows and 256 columns. One redundant column would therefore be able to replace one of the 256 columns, thus constituting an efficient use of a redundant circuit.
One problem encountered in replacing a column or row in a semiconductor memory is maintaining address integrity; that is, the redundant column must have the same address as the defective column. This is normally implemented by providing a universal decode circuit in association with the redundant column circuitry. Appropriate fuses are included that can be opened to both activate the redundant column circuitry and also to program the universal decode circuitry for the appropriate address.
A redundant memory generally includes an array of memory cells arranged in rows and columns, each column of cells selected by a column address signal and each row of adjacent cells selected by a row address signal. A redundant column of memory elements is disposed adjacent the array and is selectable by a predetermined column address with the redundant column memory normally inactive. When a column of memory cells in the array is determined to be defective, this column is deactivated and a circuit is provided for activating the redundant column, such that it can be addressed by the predetermined column address. The addresses of the columns that are physically disposed between the defective column and the redundant column are reconfigured and incremented by one towards the defective column address.
Prior art universal decode circuitry for reconfiguring the addresses of the columns located between the defective column and redundant column typically includes a non-reconfigurable redundancy configuration circuit which is programmed once with a RAM redundancy map that is used to configure the active memory columns whenever the chip is powered up. During manufacturing test, the failing column must be identified, and the appropriate redundancy map stored in the redundancy configuration circuit. The redundancy configuration circuit is conventionally implemented with a bank of fuses, one per column that can be reconfigured. The corresponding fuse of each column whose address is to be reconfigured is broken in order to bypass the normal path to that column. Thus, during power up of the chip, a signal is fired which loads the redundancy map into redundancy registers that control the switches in the universal decode circuitry.
The conventional method for programming a RAM redundancy map requires off-line resources to program the redundancy configuration circuit (i.e., to break the fuses). This can be a time-consuming process that requires expensive equipment and/or costly technician time. In addition, because a single fuse is used for each reconfigurable column in memory, the number of fuses required to provide RAM redundancy may be quite large. Due to the sizes of the fuses, a high-density RAM may not be able to accommodate the number of required fuses in terms of space.
Accordingly, a need exists for a method for automatically programming a redundancy map for a RAM, and for redundant circuits in general, without the assistance of external resources. A need also exists for a method for reducing the size and cost of the redundancy configuration circuit.